1. Field of the Invention
This invention relates to a computer and, more particularly, to an apparatus and method for detecting, during computer reset, the size of a contiguous physical memory size residing within one or more memory banks inserted into the computer.
2. Description of the Related Art
Modern microprocessors and/or computers address according to byte granularity. This means memory is generally organized and accessed as a sequence of bytes, and a byte address is used to address memory. Byte addressable memory encompasses what is generally referred to as memory address space.
The memory address space, and therefore processors operating from that space, can be segmented. Segmented addressing supports programs operating from separate and distinct address segments. For example, a program can keep its code (instructions), stack addresses, data and various global or local descriptor tables in separate segments independent from one another. This allows the execution environment within each of the various segments to operate independent of one another to achieve multi-tasking.
The execution environment of each segment can be paged. Paging is a mechanism of memory management which allows the most recently accessed pages to be held in physical memory instead of slower disk space. As such, physical memory herein refers to semiconductor memory involving a rather large contiguous address space which can be written to and read from. Generally speaking, physical memory may refer to random access memory (RAM). A benefit of paging is the ability to swap byte addressable space between physical memory and disk storage, where more recently addressed memory is chosen to reside in RAM rather than disk storage.
The location of pages, often referred to as page frames, reside in physical memory and is contained in a two-system data structure--a page directory and a page table. When coupled with segmentation, paging provides a mechanism for implementing a conventional demand-paged, virtual-memory system where sections of a program's execution environment are mapped into physical memory as needed. As such, paging allows a data structure to partly reside in physical memory and partly within disk storage. To minimize the number of bus cycles required for address translation, the most recently accessed page directory and page table entries can be cached in the processor in devices called translation lookaside buffers (TLBs).
Modern processors support several modes of operation, whereby addressing differs depending on which mode the processor currently resides. For example, a Pentium Pro.RTM. processor supports protected mode and real mode addressing schemes. In real mode, the microprocessor can address a limit of 1 Mbyte of real mode memory. However, in protected mode, the addressable memory can be extended to 4 Gbytes. The Pentium Pro.RTM. microprocessor resides in real mode following power-up or reset. However, a flag can thereafter be set in the control register of the processor to determine if the processor is to operate in protected mode.
Although protected mode allows the microprocessor to access more than 1 Mbytes of memory, many modern microprocessors such as the Pentium Pro.RTM. processor utilize an address bus exceeding 32 bits. This allows the address bus to access, for example, 36 bits of information comparable to 2.sup.36, or 64 Gbytes. In many server applications, it is desirable to use physical memory exceeding 4 Gbytes. However, to do so, paging is needed to translate from 4 Gbytes to 64 Gbytes. Conventional techniques for performing such translation is both time consumptive and burdensome.
Conventional paging and/or translation between a linear address space seen by a processor and physical address space of actual physical memory and disk storage occurs within page tables and page directories which form a part of, and are derived from, the physical memory. In order to translate between 4 Gbytes and 64 Gbytes, the page translation tables and directories must first be established within RAM, and then the formulated page translation tables will allow translation to the extended (greater than 4 Gbyte) range.
A problem exists, however, whenever the computer is first initialized during reset or boot up. During boot up, the computer must detect or "feel" for physical memory present within the computer. The detection process involves the processor determining physical memory size by writing to an address and reading from that address. The fact that the stored value equals the address read indicates that physical memory is present at least at that address. The concept of writing to and reading from an address proves advantageous over setting jumper wires or dual in-line package (DIP) switches.
If the translation tables are to be established in RAM, then boot up must entail detecting physical memory less than 4 Gbytes and then, from the detected memory space, establishing translation tables within a portion of that detected space. Only at this time can the extended memory range be detected from the translation tables.
The sequential operation of detecting a limited physical address range, then building translation tables within a portion of that range, and then finally detecting the remainder of the physical address space within the extended range exceeding 4 Gbytes adds significant time to the boot-up procedure. Thus, translation tables built within either cache or RAM pose significant limitations against being able to detect the entire 36-bit physical address range during a single boot-up step.